Biphasic dickson switched capacitor converters with zero voltage switching

ABSTRACT

A biphasic Dickson switched capacitor converter with zero voltage switching is provided. The biphasic Dickson switched capacitor converter introduces an auxiliary circuit between middle points of two freewheeling bridge arms of a conventional biphasic Dickson converter, and charges at a middle point of a first freewheeling bridge arm are transferred to a second freewheeling bridge arm by controlling the auxiliary circuit during a dead time when main power transistors are turned off to realize zero voltage switching of the main power transistors and reduce a switching loss. An on-resistance of an introduced auxiliary power transistor is larger than an on-resistance of the main power transistors. An inductance value of an auxiliary inductor is small and a package size and cost are low. Therefore, the biphasic Dickson switched capacitor converter reduces the switching loss of switched capacitor converter, improve efficiency, have performance benefits and commercial prospects by introducing the auxiliary circuit.

CROSS REFERENCE TO THE RELATED APPLICATIONS

This application is based upon and claims priority to Chinese Patent Application No. 202111353958.5, filed on Nov. 12, 2021, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention belongs to the field of switching power supplies, and particularly relates to a biphasic Dickson switched capacitor converter with zero voltage switching.

BACKGROUND

Conventional inductive DC-DC converters (buck, boost, buck-boost, etc.) are widely used in 5G base station/server power supply/mobile phone motherboard to achieve the conversion between different voltages. However, inductive converters are generally inefficient due to large switching loss and inductive loss. For applications such as high power consumption 5G communication and high power fast charging of mobile phones, the efficiency of the converter is required to be high due to heat dissipation considerations. Conventional inductive converters have failed to meet efficiency requirements.

Since the energy density of capacitors is higher than that of inductors, the efficiency of switched capacitor converters using capacitors for energy transmission is much higher than that of inductors, which are widely used in various high efficiency scenarios. And cascade type switched capacitor converters are widely used in a wide variety of switched capacitor converter topology architectures because of their low equivalent impedance.

As shown in FIG. 1 , an existing biphasic Dickson-type 4:1 switched capacitor converter comprises 12 power transistors (Q1/Q2/Q3/Q4/Q5A/Q5B/Q6A/Q6B/Q7A/Q7B/Q8A/Q8B); six flying capacitors (C1A/C1B/C2A/C2B/C3A/C3B); an input capacitor CIN; an output capacitor COUT and an output load IOUT. In control, Q1/Q3/Q5A/Q7A/Q6B/Q8B are driven by the same control signal, and Q2/Q4/Q6A/Q8A/Q5B/Q7B are by with the same control signal. Both control signals are 50% duty ratio square wave signals, complementary in waveform. The converter can realize that the output voltage VOUT is ¼ of the input voltage, i.e. VIN=4*VOUT. And the voltages on the six flying capacitors are VC1A=VC1B=VOUT, VC2A=VC2B=2*VOUT, VC3A=VC3B=3*VOUT, respectively.

Although the existing biphasic 4:1 Dickson switched capacitor converter has no switching-off loss and inductive loss, it still needs to overcome the two parasitic capacitors Cds and Cgd when the power transistor is turned on, and there is a certain switching-on loss. For high voltage and low current applications, the ratio of switching-on loss is larger due to the higher voltages on the two capacitors Cds and Cgd, which limits the further improvement of converter efficiency.

SUMMARY

The present invention is directed to the above-mentioned problems, and a novel biphasic switched capacitor converter with zero voltage switching-on (ZVS) is proposed, wherein the zero voltage switching-on of all main power transistors can be realized by introducing an auxiliary circuit, thereby reducing switching loss. At the same time, the topology architecture can be extended to biphasic N:1 ZVS switched capacitor converter.

The technical solution of the present invention is:

A biphasic Dickson switched capacitor converter with zero voltage switching, and two freewheeling bridge arms are provided on two sides of an output end of a topology structure of the biphasic Dickson switched capacitor converter, and a power transistor in the biphasic Dickson switched capacitor converter is defined as a main power transistor, wherein a control auxiliary circuit is provided between the two freewheeling bridge arms, and the control auxiliary circuit is used for transferring the charges on one freewheeling bridge arm to the other bridge arm during a dead time when all the main power transistors are turned off, so that voltages at two ends of the main power transistor become zero, thereby achieving zero voltage switching-on of all the main power transistors.

A specific structure of a biphasic 4:1 ZVS switched capacitor converter is firstly proposed in the present invention, specifically comprising a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor; wherein one end of the eighth power transistor is connected to an external input voltage, the other end of the eighth power transistor is connected to one end of the seventh power transistor and one end of the third capacitor, one end of the twelfth power transistor is connected to the external input voltage, and the other end of the twelfth power transistor is connected to one end of the eleventh power transistor and one end of the sixth capacitor; the other end of the seventh power transistor is connected to one end of the sixth power transistor and one end of the fifth capacitor, and the other end of the eleventh power transistor is connected to one end of the tenth power transistor and one end of the second capacitor; the other end of the sixth power transistor is connected to one end of the fifth power transistor and one end of the first capacitor, and the other end of the tenth power transistor is connected to one end of the ninth power transistor and one end of the fourth capacitor; the other end of the fifth power transistor is connected to one end of the second power transistor, and the other end of the ninth power transistor is connected to one end of the third power transistor; the other end of the second power transistor is connected to one end of the first power transistor, the other end of the first capacitor, the other end of the second capacitor and the other end of the third capacitor; the other end of the third power transistor is connected to one end of the fourth power transistor, the other end of the fourth capacitor, the other end of the fifth capacitor and the other end of the sixth capacitor; and a connection point of the fifth power transistor, the second power transistor, the third power transistor and the ninth power transistor is an output end; and two freewheeling bridge arms are respectively defined as a first freewheeling bridge arm and a second freewheeling bridge arm, and a connection point of the first power transistor, the second power transistor, the first capacitor, the second capacitor and the third capacitor is the middle point of the first freewheeling bridge arm, and a connection point of the third power transistor, the fourth power transistor, the fourth capacitor, the fifth capacitor and the sixth capacitor is the middle point of the second freewheeling bridge arm;

the control auxiliary circuit comprises a thirteenth power transistor, a fourteenth power transistor, a fifteenth power transistor, a sixteenth power transistor and an inductor; wherein one end of the thirteenth power transistor is connected to the middle point of the first freewheeling bridge arm, the other end of the thirteenth power transistor is connected to one end of the inductor and one end of the fourteenth power transistor, and the other end of the fourteenth power transistor is grounded; the other end of the inductor is connected to one end of the fifteenth power transistor and one end of the sixteenth power transistor, the other end of the fifteenth power transistor is grounded, and the other end of the sixteenth power transistor is connected to the middle point of the second freewheeling bridge arm.

Since the by-phase N:1 ZVS converter topology architecture and the structures of the two freewheeling bridge arms of the above-mentioned by-phase 4:1 ZVS converter topology architecture are in a similar way, the control auxiliary circuit in the above-mentioned solution can be directly applied to the by-phase N:1 ZVS converter.

The working sequence for a biphasic 4:1 switched capacitor converter with zero voltage switching comprises four stages as follows:

-   a first stage: the second power transistor, the fourth power     transistor, the sixth power transistor, the eighth power transistor,     the ninth power transistor, the eleventh power transistor, the     fourteenth power transistor and the sixteenth power transistor are     turned on, and the other power transistors are turned off; the first     capacitor, the third capacitor and the fifth capacitor are enabled     to be in charge state, the second capacitor, the fourth capacitor     and the sixth capacitor are in discharge state, and the inductive     current is 0 in the first stage; -   a second stage: the thirteenth power transistor and the sixteenth     power transistor are turned on, and the other power transistors are     turned off; the inductive current firstly increases and then     decreases in the second stage, and the second stage ends when the     inductive current decreases to 0; -   a third stage: the first power transistor, the third power     transistor, the fifth power transistor, the seventh power     transistor, the tenth power transistor, the twelfth power     transistor, the thirteenth power transistor and the fifteenth power     transistor are turned on, and the other power transistors are turned     off; the first capacitor, the third capacitor and the fifth     capacitor are enabled to be in discharge state, the second     capacitor, the fourth capacitor and the sixth capacitor are in     charge state, and the inductive current is 0 in the third stage; -   a fourth stage: the thirteenth power transistor and the sixteenth     power transistor are turned on, and the other power transistors are     turned off; the inductive current first increases and then decreases     in the fourth stage, and the fourth stage ends when the inductive     current decreases to 0, and the first stage is returned.

The above-mentioned solution is a control sequence, and there are, of course, other control sequences on the basis of the above-mentioned circuit structure.

The advantageous effects of the present invention are: the present invention introduces an auxiliary circuit (comprising four power transistors and an inductor) between the middle points of two freewheeling arms at outer side of a conventional biphasic Dickson converter. The charges at the middle point of one freewheeling bridge arm can be transferred to the other bridge arm by controlling the auxiliary circuit during the dead time when all main power transistors are turned off, so as to realize zero voltage switching (zvs) of all main power transistors and reduce the switching loss. The on-resistance of the introduced auxiliary power transistor is much larger than the on-resistance of the main power transistor, and the cost is very low. The inductance value of the auxiliary inductor is small and the package size and cost are also very low. Therefore, the present invention can significantly reduce the switching loss of a switched capacitor converter, improve efficiency, have good performance benefits and commercial prospects by introducing an auxiliary circuit with very low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing the structure of a conventional biphasic 4:1 switched capacitor converter.

FIG. 2 is a schematic diagram showing the structure of a biphasic 4:1 switched capacitor converter of the present invention.

FIG. 3 is a typical waveform diagram of a biphasic 4:1 ZVS switched capacitor converter of the present invention.

FIG. 4 is an equivalent circuit diagram of a biphasic 4:1 ZVS switched-capacitor converter of the present invention operating in Stage 0.

FIG. 5 is an equivalent circuit diagram of a biphasic 4:1 ZVS switched capacitor converter of the present invention working in Stage 1.

FIG. 6 is an equivalent circuit diagram of a biphasic 4:1 ZVS switched capacitor converter of the present invention working in Stage 2.

FIG. 7 is an equivalent circuit diagram of a biphasic 4: 1 ZVS switched capacitor converter of the present invention working in Stage 3.

FIG. 8 is a schematic diagram of a biphasic N:1 ZVS switched capacitor converter according to the present invention.

FIG. 9 is a schematic diagram showing the structures of various auxiliary ZVS circuits.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, the present invention will be described in detail with reference to the drawings.

As shown in FIG. 2 , the novel biphasic 4:1 ZVS switched capacitor converter proposed by the present invention comprises a main power circuit and an auxiliary ZVS circuit. Wherein the main power part comprises 12 main power transistors (Q1/Q2/Q3/Q4/Q5A/Q5B/Q6A/Q6B/Q7A/Q7B/Q8A/Q8B), 6 flying capacitors (C1A/C1B/C2A/C2B/C3A/C3B), an input capacitor CIN, an output capacitor COUT and an output load IOUT. The auxiliary circuit comprises four auxiliary power transistors (QX1A/QX2A/QX1B/QX2B), and an auxiliary inductor L.

In steady state working conditions, VIN=4*VOUT, VC1A=VC1B=VOUT, VC2A=VC2B=2*VOUT, VC3A=VC3B=3*VOUT.

FIG. 3 shows working waveform of the novel biphasic 4:1 ZVS switched capacitor converter in one switching cycle. There are four working states in sequence within one working cycle, namely stage 0, stage 1, stage 2 and stage 3. The signal PHA is an original clock signal with a 50% duty ratio; the signal PHB is an inverse signal of the PHA; the signal PHA_DLY is a clock signal obtained by the PHA after a delay; the signal PHB_DLY is a clock signal obtained by PHB after a delay. The signals Q1/Q3/Q5A/Q7A/Q6B/Q8B are the on-off states of the main power switches Q1/Q3/Q5A/Q7A/Q6B/Q8B and the signals Q2/Q4/Q6A/Q8A/Q5B/Q7B are the on-off states of the main power switches Q2/Q4/Q6A/Q8A/Q5B/Q7B. The signals QX1A/QX2A/QX1B/QX2B are the on-off states of the auxiliary switching transistors QX1A/QX2A/QX1B/QX2B respectively, the signals CFLA/CFLB are the voltage waveforms of the node CFLA and node CFLB respectively, LXA/LXB are the voltage waveforms of the node LXA and node LXB respectively, and iL is the current waveform flowing through the inductor L.

Stage 0 (t0-t1)

As shown in FIG. 4 , in stage 0, the main power transistors Q2/Q4/Q6A/Q8A/Q5B/Q7B are turned on and the main power transistors Q1/Q3/Q5A/Q7A/Q6B/Q8B are turned off. The flying capacitors C1A/C2B/C3A are in charge state and the flying capacitors C1B/C2A/C3B are in discharge state. In the auxiliary circuit part, auxiliary transistors QX1B and QX2A are turned on, and QX1A and QX2B are turned off. In this stage, the node CFLA voltage is equal to the output voltage, the node CFLB voltage is zero, the voltages of the node LXA and node LXB are zero, and the current flowing through the inductor L is zero.

Stage 1 (t1-t2)

As shown in FIG. 5 , at the moment t1, the main power transistors Q2/Q4/Q6A/Q8A/Q5B/Q7B are turned off, and at this point, all 12 main power transistors are turned off. The flying capacitors C1A/C1B/C2A/C2B/C3A/C3B stop charging or discharging and maintain the current voltages. The load current is provided by discharging the output capacitor. The auxiliary transistor QX2A is turned off and QX1A is turned on.

Before the moment t1, the CFLA node voltage is VOUT and the CFLB node voltage is zero. From the moment t1, the inductor L is connected between CFLA and CFLB, when the parasitic capacitor of the CFLA node and the parasitic capacitor of the CFLB node and the inductor L start to resonate. The resonance of the CFLA node voltage decreases, the resonance of the CFLB node voltage increases, and the current of the inductor L gradually increases. When the CFLA voltage and the CFLB voltage are the same, the current through the inductor peaks. Thereafter, the CFLA node voltage continues to decrease, the CFLB node voltage continues to increase, and the inductive current begins to decrease. By the moment t2, the CFLA node voltage resonates to zero voltage, the CFLB node voltage resonates to VOUT voltage, and the inductive current decreases to zero. At this point stage 2 is entered.

It can be seen that the charges of the CFLA node can be transferred to the CFLB node using the resonance between the inductor and the parasitic capacitor in stage 1. The ZVS switching condition is thus provided for the main power transistors Q1/Q3/Q5A/Q7A/Q6B/Q8B to be turned on in the next stage.

Stage 2 (t2-t3)

As shown in FIG. 6 , at the moment t2, the main power transistors Q1/Q3/Q5A/Q7A/Q6B/Q8B are turned on at zero voltages and the main power transistors Q2/Q4/Q6A/Q8A/Q5B/Q7B remain off. The auxiliary transistor QX2B is turned on and QX1B is turned off. The converter proceeds to stage 2. The flying capacitors C1A/C2B/C3A are in discharge state and the flying capacitors C1B/C2A/C3B are in charge state. The node CFLA voltage is zero, the node CFLB voltage is equal to the output voltage, the voltages of the node LXA and node LXB are zero, and the current flowing through the inductor L is zero.

Stage 3 (t3-t4)

As shown in FIG. 7 , at the moment t3, the main power transistors Q1/Q3/Q5A/Q7A/Q6B/Q8B are turned off, and all eight main power transistors are turned off. The flying capacitors C1/C2/C3 stop charging or discharging and maintain the current voltages. The load current is provided by discharging the output capacitor. The auxiliary transistor QX2B is turned off and QX1B is turned on.

Before the moment t3, the CFLA node voltage is zero and the CFLB node voltage is the output voltage. From the moment t3, the inductor L is connected between the CFLA and the CFLB, when the parasitic capacitor of the CFLA node and the parasitic capacitor of the CFLB node and the inductor L start to resonate. The resonance of the CFLA node voltage increases, the resonance of the CFLB node voltage decreases, and the current of the inductor L gradually increases in negative direction. When the CFLA voltage and the CFLB voltage are the same, the current through the inductor reaches a negative peak. Thereafter, the CFLA node voltage continues to increase, the CFLB node voltage continues to decrease, and the inductive current begins to decrease in negative direction. By the moment t0, the CFLA node voltage resonates to the output voltage, the CFLB node voltage resonates to zero, and the inductive current decreases to zero. At this point the stage 0 is entered.

It can be seen that the charges of the CFLB node can be transferred to the CFLA node by resonance between inductor and parasitic capacitors in stage 3. The ZVS switching condition is thus provided for the main power transistors Q2/Q4/Q6A/Q8A/Q5B/Q7B to be turned on in the next stage.

The structure of the present invention controls the switches QX1A, QX2A, QX1B and QX2B through the above-mentioned control sequence to transfer the charges on the node CFLA to the node CFLB via the inductor L within the stage 1, and to transfer the charges on the node CFLB to the node CFLA via the inductor L within the stage 3, so that the voltages of the both ends of the main power switches Q1, Q2, Q3, Q4, Q5A, Q5B, Q6A, Q6B, Q7A, Q7B, Q8A and Q8B are zero before the switches are turned on, which greatly reduces the switching loss and improves the conversion efficiency of the switched capacitor converter.

On the basis of the novel biphasic 4:1 ZVS switched capacitor converter shown in FIG. 2 , a biphasic N:1 ZVS switched capacitor converter can be realized by introducing main power transistors and flying capacitors, as shown in FIG. 8 . The same auxiliary ZVS circuit as in FIG. 2 and a similar control mode can be used in the converter to achieve zero voltage switching of all main power transistors. Wherein N is an integer which is greater than or equal to 4.

The auxiliary ZVS circuit shown in FIG. 2 comprises four NMOS and an inductor, and it can be realized that the charges at the middle point of one freewheeling bridge arm can be transferred to the other bridge arm by controlling the auxiliary circuit during the dead time when all the main power transistors are turned off, so as to realize zero voltage switching of all the main power transistors and reducing switching loss. Besides the auxiliary ZVS circuit of FIG. 2 , which can perform this function, various other types of circuits can also perform the function of the ZVS. A variety of different auxiliary ZVS circuits are as shown in FIG. 9 , and thus it can be proved that the specific implementations of the circuits are diverse, and various modifications, variations or equivalents of the above examples can be readily envisioned by those skilled in the art after understanding the present disclosure, and still be subject to the limitations set forth in the claims and any equivalents thereof. 

What is claimed is:
 1. A biphasic Dickson switched capacitor converter with zero voltage switching, wherein two freewheeling bridge arms comprising a first freewheeling bridge arm and a second freewheeling bridge arm are provided on two sides of an output end of a topology structure of the biphasic Dickson switched capacitor converter, and a power transistor in the biphasic Dickson switched capacitor converter is defined as a main power transistor, wherein a control auxiliary circuit is provided between the two freewheeling bridge arms, and the control auxiliary circuit is used for transferring charges on the first freewheeling bridge arm to the second freewheeling bridge arm during a dead time when main power transistors are turned off, wherein voltages at two ends of the main power transistors become zero to achieve zero voltage switching of the main power transistors.
 2. The biphasic Dickson switched capacitor converter according to claim 1, wherein the biphasic Dickson switched capacitor converter is a biphasic 4:1 switched capacitor converter with zero voltage switching, comprising a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a ninth power transistor, a tenth power transistor, an eleventh power transistor, a twelfth power transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor; wherein a first end of the eighth power transistor is connected to an external input voltage, a second end of the eighth power transistor is connected to a first end of the seventh power transistor and a first end of the third capacitor, a first end of the twelfth power transistor is connected to the external input voltage, and a second end of the twelfth power transistor is connected to a first end of the eleventh power transistor and a first end of the sixth capacitor; a second end of the seventh power transistor is connected to a first end of the sixth power transistor and a first end of the fifth capacitor, and a second end of the eleventh power transistor is connected to a first end of the tenth power transistor and a first end of the second capacitor; a second end of the sixth power transistor is connected to a first end of the fifth power transistor and a first end of the first capacitor, and a second end of the tenth power transistor is connected to a first end of the ninth power transistor and a first end of the fourth capacitor; a second end of the fifth power transistor is connected to a first end of the second power transistor, and a second end of the ninth power transistor is connected to a first end of the third power transistor; a second end of the second power transistor is connected to a first end of the first power transistor, a second end of the first capacitor, a second end of the second capacitor and a second end of the third capacitor; a second end of the third power transistor is connected to a first end of the fourth power transistor, a second end of the fourth capacitor, a second end of the fifth capacitor and a second end of the sixth capacitor; a connection point of the fifth power transistor, the second power transistor, the third power transistor and the ninth power transistor is an output end; the two freewheeling bridge arms are respectively defined as the first freewheeling bridge arm and the second freewheeling bridge arm, and a connection point of the first power transistor, the second power transistor, the first capacitor, the second capacitor and the third capacitor is a middle point of the first freewheeling bridge arm, and a connection point of the third power transistor, the fourth power transistor, the fourth capacitor, the fifth capacitor and the sixth capacitor is a middle point of the second freewheeling bridge arm; the control auxiliary circuit comprises a thirteenth power transistor, a fourteenth power transistor, a fifteenth power transistor, a sixteenth power transistor and an inductor; wherein a first end of the thirteenth power transistor is connected to the middle point of the first freewheeling bridge arm, a second end of the thirteenth power transistor is connected to a first end of the inductor and a first end of the fourteenth power transistor, and a second end of the fourteenth power transistor is grounded; a second end of the inductor is connected to a first end of the fifteenth power transistor and a first end of the sixteenth power transistor, a second end of the fifteenth power transistor is grounded, and a second end of the sixteenth power transistor is connected to the middle point of the second freewheeling bridge arm.
 3. The biphasic Dickson switched capacitor converter according to claim 2, wherein a working sequence of the biphasic 4:1 switched capacitor converter with zero voltage switching comprises four stages as follows: a first stage: the second power transistor, the fourth power transistor, the sixth power transistor, the eighth power transistor, the ninth power transistor, the eleventh power transistor, the fourteenth power transistor and the sixteenth power transistor are turned on, and remaining power transistors are turned off; the first capacitor, the third capacitor and the fifth capacitor are enabled to be in a charge state, the second capacitor, the fourth capacitor and the sixth capacitor are in a discharge state, and an inductive current is 0 in the first stage; a second stage: the thirteenth power transistor and the sixteenth power transistor are turned on, and remaining power transistors are turned off; the inductive current firstly increases and then decreases in the second stage, and the second stage ends when the inductive current decreases to 0; a third stage: the first power transistor, the third power transistor, the fifth power transistor, the seventh power transistor, the tenth power transistor, the twelfth power transistor, the thirteenth power transistor and the fifteenth power transistor are turned on, and remaining power transistors are turned off; the first capacitor, the third capacitor and the fifth capacitor are enabled to be in the discharge state, the second capacitor, the fourth capacitor and the sixth capacitor are in the charge state, and the inductive current is 0 in the third stage; a fourth stage: the thirteenth power transistor and the sixteenth power transistor are turned on, and remaining power transistors are turned off; the inductive current first increases and then decreases in the fourth stage, and the fourth stage ends when the inductive current decreases to 0, and the first stage is returned. 